1. Field of the Invention
The present invention relates to a wiring substrate and a method of manufacturing the same and a semiconductor device and, more particularly, a wiring substrate in which solder layers are provided on connection pads to which a semiconductor chip is flip-chip connected, and a method of manufacturing the same and a semiconductor device.
2. Description of the Related Art
In the prior art, a wiring substrate on which a semiconductor chip is flip-chip mounted is provided. As the approach of flip-chip mounting the semiconductor chip, there is such an approach that a solder is formed in advance on connection pads of the wiring substrate and then bumps of the semiconductor chip are joined to the connection pads of the wiring substrate via the solders. In order to attain sufficient joining strength between the bumps of the semiconductor chip and the connection pads of the wiring substrate, a sufficient volume of solder must be ensured on the connection pads of the wiring substrate.
In FIG.1, a state of connection pads of a wiring substrate in the prior art is illustrated. As shown in FIG.1, in a wiring substrate 100, a plurality of wirings 200 equipped with a connection pad 220 respectively are formed on an interlayer insulating layer 300, and a solder resist 400 in which an opening portion 400a is provided on an area that contains the connection pads 220 of a plurality of wirings 200 is formed.
Each of the wirings 200 exposed from the opening portion 400a of the solder resist 400 is constructed by the connection pad 220 arranged in a center portion, and a leading wiring portion 240 connected vertically to upper and lower ends of the connection pad 220 respectively. The leading wiring portion 240 together with the connection pad 220 is arranged linearly to extend in the same direction as the longitudinal direction of the connection pad 220. Also, a width WA of the connection pad 220 is set thicker than a width WB of the leading wiring portion 240.
Then, the protrusive solder layer is formed on the connection pads of the wiring substrate respectively. As the method of forming the solder layer, a solder is formed on the wirings 200 (the leading wiring portions 240 and the connection pads 220), which are exposed from the opening portion 400a of the solder resist 400, as a pattern and then a reflow heating is applied to the solder.
At this time, as shown in FIG.2, when the solder is melted, the solder on the leading wiring portion 240 is moved onto the wide connection pad 220 by a surface tension of the solder. Thus, the solder is arranged concentratedly onto the connection pad 220. In this way, the solder layer having a required volume (shaded portion) is formed on the connection pad 220 to protrude upward.
As the similar technology, in Patent Literature 1 (Patent Application Publication (KOKAI) 2000-77471), it is set forth that, in the flip-chip mounting substrate on which an electronic component is mounted, the wiring pattern and the connection pads are exposed from openings of a solder resist, and a width of the connection pad is set larger than a width of the wiring pattern, and then solder bumps are formed while causing the solder on the wiring pattern to concentrate on the connection pad.
Also, in Patent Literature 2 (Patent Application Publication (KOKAI) 2004-40056), it is set forth that miniaturization of wiring patterns is attained by using curved bump receiving pads and straight pattern lines, and also respective exposed areas of the bump receiving pads are made equal by removing the resist, which is provided on the bump receiving pads and the pattern lines, in the same cylindrical shape, whereby a variation of height of the conductive bumps formed on the bump receiving pads is prevented.
In Patent Literature 3 (Patent Application Publication (KOKAI) Hei 7-94853), such a solder coating method is set forth that solder powders are adhered selectively to pre-coated portions of metal terminals of a printed-wiring board, then a flux is coated thereon, and then the solder powders are melted by the reflow heating.
In recent years, a pitch of the pads is narrowed along with performance enhancement of the semiconductor chip, and correspondingly a narrowing of a pitch of the connection pads of the wiring substrate is demanded. In the foregoing prior art, in order to arrange the solder stably on the connection pads 220 by utilizing a surface tension of the solder, the width WA of the connection pad 220 must be set thicker than the width WB of the leading wiring portion 240 by almost several tens μm.
This is because, unless the width WA of the connection pad 220 is not set sufficiently thicker than the width WB of the leading wiring portion 240, the solder is arranged in the position that is displaced from the center portion of the connection pad 220 or the height of the solders varies.
When a minimum pitch which can be formed is 40 μm (line:space=20 μm:20 μm) in forming the wirings of the wiring substrate, it is difficult to miniaturize the space. Therefore, the pitch of the wiring must be extended as much as the amount that the width of the connection pad becomes thick.
For example, in above FIG. 1, when the width WA of the connection pad 220 is set thicker than the width WB of the leading wiring portion 240 by 15 μm, even though the minimum pitch of the wirings which can be formed is 40 μm, the pitch of the wirings is increases to 55 μm (line:space=35 μm:20 μm).
This means that, unless an ability of the patterning technology based on the photography is improved, the patterning cannot respond to a narrow pitch smaller than the above. Thus, there is a problem that it can not easily respond to the further narrowing of the pitch of the pads of a semiconductor chip.